1. Field of the Invention
The present invention relates to memory circuits and, in particular, to memory circuits with nonvolatile memories.
2. Discussion of Related Art
Sequential logic circuits are utilized in numerous systems. Currently, logic circuits and processors based on these sequential circuits consume high amounts of power. Further, it is expected that the power consumption will increase with decreasing dimensions of semiconductor components utilized in the sequential logic circuit. In particular, in the generation after the current MOSFET 65 nm technology, it is expected that static power consumption due to gate electrode leakage will become larger than the dynamic power consumption due to turning on and off of MOSFET transistors.
Conventional methods for decreasing power consumption of a circuit based on MOSFETs involves the use of two kinds of MOSFETs having different threshold voltages or involves regulation of the threshold voltage of MOSFETs by controlling substrate bias and supply voltage. However, the reduction of supply voltage should be limited in these methods because data stored in volatile memory cells may be easily lost when supply voltages are reduced. Further, static gate leakage, which increases as the gate oxide becomes thinner, is inevitable. Therefore, the real effects of these types of power consumption reducing techniques are limited.
A more effective method of reducing the power consumption of a sequential logic circuit is to shut the voltage off to that circuit completely. This technique is not possible in conventional sequential logic circuits because, as soon as the power is shut off, the data stored in the circuit is lost. A proposed memory system for reducing the power in this manner is shown in FIG. 1. A Memory cell 100 shown in FIG. 1 is proposed in IEICE Technical Report ICD 2002-10 (2002) p. 13 (Japan). Memory cell 100 represents a D-latch type of memory circuit, in which data can be stored in cross-coupled inverters 102 and 104. Transmission gates 101 and 103 provide voltages to a storage cell 110 in accordance with a clock signal CK and thereby can act as switches. A transmission gate 105 is coupled between inverters 102 and 104. Ferroelectric memory cells 107 and 106 are coupled from either side of inverter 104 to a plate line 108. Ferroelectric memory cell 107 is coupled between one terminal of inverter 104 and plate line 108 and ferroelectric memory cell 106 is coupled between the opposite terminal of inverter 104 and plate line 108.
Digital data is stored in memory cell 100 by applying voltages to ferroelectric memory cells 107 and 106 through plate line 108. Due to the difference between the amount of charge on ferroelectric cell 107 versus the amount of charge on ferroelectric cell 106, the data stored in ferroelectric memory cells 107 and 106 is transferred to volatile storage cell 110 when power is re-applied to memory cell 100. Data from storage cell 110 is written into nonvolatile ferroelectric memory cells 107 and 106 when sufficient voltage is applied to plate line 108.
Many ferroelectric materials used in Ferroelectric memory cells, however, exhibit poor endurance when subjected to repeated write/erase operations. In many cases, the endurance is limited to about 1014 operations even for high quality ferroelectric materials formed directly on a silicon substrate. The endurance may be seriously degraded for ferroelectric materials stacked on silicon devices on a silicon substrate. Because memories in logic circuits are repeatedly rewritten in accordance with the clock signal, a typical number of operations exceeds 1014 in a single month of operation in a 100 MHz clock, after which the logic circuits may become unreliable or no longer function.
In addition to the endurance difficulties, high quality ferroelectric materials are only formed directly on a silicon substrate and cannot easily be stacked. Additionally, memory cell 100 includes additional plate lines 108 and other circuits for control of the plate line voltages needed to write data to the memory cell. Consequently, the area utilized by memory cell 100 can become large.
Therefore, there is a need for memory cells that can easily store data while being powered down in order to reduce the power usage of sequential logic circuits or other data storage circuits.